STMPE811_08 datasheet(9/54 Pages) STMICROELECTRONICS

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STMPE811

I2C interface

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4.1

I2C features

The features that are supported by the I2C interface are listed below:

●

I2C slave device

●

Operates at 1.8 V

●

Compliant to Philips I2C specification version 2.1

●

Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes

Start condition

A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.

A Start condition must precede any data/command transfer. The device continuously

monitors for a Start condition and does not respond to any transaction unless one is

encountered.

Stop condition

A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A

Stop condition terminates communication between the slave device and the bus master. A

read command that is followed by NoAck can be followed by a Stop condition to force the

slave device into idle mode. When the slave device is in idle mode, it is ready to receive the

next I2C transaction. A Stop condition at the end of a write command stops the write

operation to registers.

Acknowledge bit

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter

releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls

the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave

the SDATA in high state if it does not acknowledge the receipt of the data.

Table 6.

I2C timing

Symbol

Parameter

Min

Typ

Max

Uni

fSCL

SCL clock frequency

400

kHz

tLOW

Clock low period

1.3

tHIGH

Clock high period

600

SDA and SCL fall time

300

tHD:STA

START condition hold time (after this

period the first clock is generated)

600

tSU:STA

START condition setup time (only relevant

for a repeated start period)

600

tSU:DAT

Data setup time

100

tHD:DAT

Data hold time

tSU:STO

STOP condition setup time

600

tBUF

Time the bus must be free before a new

transmission can start

1.3

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