| 전자부품 데이터시트 검색엔진 |
|
74V1T07STR 데이터시트(PDF) 1 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
74V1T07STR 데이터시트(HTML) 1 Page - STMicroelectronics |
|
1 / 9 page ![]() 1/9 April 2004 s HIGH SPEED: tPD = 4.3ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =1µA(MAX.) at TA=25°C s COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN), VIL =0.8V (MAX) s POWER DOWN PROTECTION ON INPUT s OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74V1T07 is an advanced high-speed CMOS SINGLE BUFFER (OPEN DRAIN) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 2 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on input and 0 to 7V can be accepted on input with no regard to the supply voltage. This device can be used to interface5V to3V. 74V1T07 SINGLE BUFFER (OPEN DRAIN) PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE T & R SOT23-5L 74V1T07STR SOT323-5L 74V1T07CTR SOT323-5L SOT23-5L |
유사한 부품 번호 - 74V1T07STR |
|
유사한 설명 - 74V1T07STR |
|
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |