STTS424E02 datasheet(36/51 Pages) STMICROELECTRONICS

36 / 51 page

Initial delivery state - SPD

STTS424E02

36/51

Initial delivery state - SPD

The device is delivered with all bits in the memory array set to ‘1’ (each byte contains FFh).

Use in a memory module

In the Dual In line Memory Module (DIMM) application, the SPD is soldered directly on to

the printed circuit module. The three Chip Enable inputs (A0, A1, A2) must be connected to

VSS or VDD directly (that is without using a pull-up or pull-down resistor) through the DIMM

socket (see Table 22).

The Write Control (WC) of the device is tied to ground to maintain full read and write access.

7.1

Programming the SPD

The situations in which the SPD EEPROM is programmed can be considered under two

headings:

●

when the DIMM is isolated (not inserted on the PCB motherboard)

●

when the DIMM is inserted on the PCB motherboard

7.1.1

DIMM isolated

With specific programming equipment, it is possible to define the SPD EEPROM content,

using Byte and Page Write instructions, and its write-protection using the SWP and CWP

instructions. To issue the SWP and CWP instructions, the DIMM must be inserted in the

application-specific slot where the A0 signal can be driven to VHV during the whole

instruction. This programming step is mainly intended for use by DIMM makers, whose end

application manufacturers will want to clear this write-protection with the CWP on their own

specific programming equipment, to modify the lower 128 bytes, and finally to set

permanently the write-protection with the PSWP instruction.

Table 22.

DRAM DIMM connections

DIMM position

VSS (0)

VSS(0)

VSS (0)

VDD (1)

VSS (0)

VDD (1)

VSS (0)

VDD (1)

VDD(1)

VDD (1)

VSS (0)

VDD (1)

VSS (0)

VDD (1)

VSS (0)

VDD (1)

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