USBLC6-2

Technical information

5/14

We can significantly reduce this phenomena with simple layout optimization. It is for this

reason that some recommendations have to be followed (see 2.3: How to ensure good ESD

protection).

Figure 6.

ESD behavior: parasitic phenomena due to unsuitable layout

2.3

How to ensure good ESD protection

While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on

the layout of the board. In the same way, with the rail to rail topology, the track from data

possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for

layout consideration)

Vpin

CC

I/O pin

V+ V

TRANSIL

F

t = 1 ns

r

t

t

t = 1 ns

r

GND pin

Data line

Positive

Surge

Negative

Surge

ESD surge on data line

di

dt

di

dt

di

dt

di

dt

di

dt

V

+ =V

+V + L

+ L

surge > 0

CL

TRANSIL

F

I/O

GND

V

= -V - L

- L

surge > 0

CL-

F

I/O

GND

di

dt

di

dt

di

dt

di

dt

di

dt

Rd.Ip

V

V

BR

TRANSIL

+

=

Figure 7.

ESD behavior: layout optimization

Figure 8.

ESD behavior: measurement

conditions

Unsuitable layout

Optimized layout

11

6

2

5

3

4

11

6

2

5

3

4

+5 V

IN

OUT

TEST BOARD

ESD SURGE