General features

VT5376

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Figure 10.

Frame dump mode timing diagram

7.5

Image streaming

To enter this test mode, set bit 4 of registry 0x62 to 1 (PCI_test_enable).

In this mode, the pins VGATE_ON, RESET_OUT, LASER_NEN and MOTION are used to

output serially fast video data in the form of 2 bits nibble + FST and QCLK.

Upon receipt of an FST (LASER_NEN) rising edge, NIB_EVEN (VGATE_ON) and

NIB_ODD (RESET_OUT) output data every 48 MHz clock cycle. The signals should be

sampled 10 ns after the FST rising edge, and then every 20.8 ns exactly, during

400 x 4 = 1600 cycles.

Groups of four consecutive NIB_EVEN and NIB_ODD must then be repackaged together to

form a single 8-bit pixel data. This format enables the pixels to be output at the same frame

rate as normal operation, and keeps I2C available to access the usual register settings.

For more details on image streaming please refer to the VT5376 image system user

manual.

frame_dump_en

frame_dump_ready

frame_dump_pixel

frame_dump_completed

0

1

2

3

398

399

pixel address

set by user

400 x I2C single reads of pixel data

set by 376

set by 376

FRAME DUMP MODE

NORMAL MODE

NORMAL MODE

reset by user