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November 2004

s

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

POWER DOWN PROTECTION ON INPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

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BALANCED PROPAGATION DELAYS:

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OPERATING VOLTAGE RANGE:

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 157

s

IMPROVED LATCH-UP IMMUNITY

s

DESCRIPTION

The 74VHC157 is an advanced high-speed

CMOS

QUAD

2-CHANNEL

MULTIPLEXER

fabricated

with

sub-micron silicon gate and

It consists of four 2-input digital multiplexer with

common

select and

strobe

inputs. It is

a

non-inverting multiplexer. When the STROBE

input is held high selection of data is inhibited and

all the outputs become

low. The

SELECT

decoding determines whether the A or B inputs

get routed to their corresponding Y outputs.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V. All inputs and outputs

are equipped with protection circuits against static

discharge, giving them 2KV ESD immunity and

transient excess voltage.

74VHC157

QUAD 2 CHANNEL MULTIPLEXER

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74VHC157MTR

TSSOP

74VHC157TTR

TSSOP

SOP

Rev. 4