| 전자부품 데이터시트 검색엔진 |
|
LD49150 데이터시트(PDF) 13 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
LD49150 데이터시트(HTML) 13 Page - STMicroelectronics |
|
13 / 20 page ![]() LD49150 Application hints 13/20 8 Application hints The LD49150 is an ultra-high performance, low dropout linear regulator, designed for high current application that requires fast transient response. The LD49150 operates from two input voltages, to reduce dropout voltage. The LD49150 is designed so that a minimum of external component are necessary. 8.1 Input supply voltage (VIN) VIN provides the power input current to the LD49150. The minimum input voltage can be as low as 1.4V, allowing conversion from very low voltage supplies to achieve low output voltage levels with very low power dissipation. 8.2 Bias supply voltage (VBIAS) The LD49150 control circuitry is supplied the VBIAS pin which requires a very low bias current (3mA typ.) even at the maximum output current level (1.5A). A bypass capacitor on the bias pin is recommended to improve the performance of the LD49150 during line and load transient. The small ceramic capacitor from VBIAS to ground reduces high frequency noise that could be injected into the control circuitry from the bias rail. In typical applications a 1µF ceramic chip capacitor may be used. The VBIAS input voltage must be 2.1V above the output voltage, with a minimum VBIAS input voltage of 3V. 8.3 External capacitors To assure regulator stability, input and output capacitors are required as shown in the typical application circuit. 8.4 Output capacitor The LD49150 requires a minimum output capacitance to maintain stability. A ceramic chip capacitor of at least 1µF is required. However, specific capacitor selection could be needed to ensure the transient response. A 1µF ceramic chip capacitor satisfies most applications but 10µF is recommended to ensure better transient performances. In applications where the VIN level is close to the maximum operating voltage (VIN>4V), it is strongly recommended to use an output capacitors of, at least, 10µF in order to avoid over-voltage stress on the Input/output power pins during short circuit conditions due to parasitic inductive effect. The output capacitor must be located as close as possible to the output pin of the LD49150. The ESR (equivalent series resistance) of the output capacitor must be within the "STABLE" region as shown in the typical characteristics figures. Both ceramic and tantalum capacitors are suitable. 8.5 Minimum load current The LD49150 does not require a minimum load to maintain output voltage regulation. |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |