LRIS2K_08 datasheet(24/102 Pages) STMICROELECTRONICS

부품명	LRIS2K

상세설명	2048-bit EEPROM tag IC at 13.56 MHz, with 64-bit UID and Password, ISO15693 and ISO18000-3 Mode 1 compliant

PDF	102 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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24 / 102 page

Data rate and data coding

LRIS2K

24/102

5.3

VCD to LRIS2K frames

Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are

implemented using code violation. Unused options are reserved for future use.

The LRIS2K is ready to receive a new command frame from the VCD 311.5 µs (t2) after

sending a response frame to the VCD.

The LRIS2K takes a power-up time of 0.1 ms after being activated by the powering field.

After this delay, the LRIS2K is ready to receive a command frame from the VCD.

5.4

Start of frame (SOF)

The SOF defines the data coding mode the VCD is to use for the following command frame.

The SOF sequence described in Figure 9 selects the 1 out of 256 data coding mode. The

SOF sequence described in Figure 10 selects the 1 out of 4 data coding mode. The EOF

sequence for either coding mode is described in Figure 11.

Figure 9.

SOF to select 1 out of 256 data coding mode

Figure 10.

SOF to select 1 out of 4 data coding mode

AI06661

37.76µs

9.44µs

37.76µs

AI06660

37.76µs

9.44µs

37.76µs

9.44µs

LRIS2K 데이터시트(PDF) 24 Page - STMicroelectronics