L6713ATR datasheet(47/64 Pages) STMICROELECTRONICS

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L6713A

Output voltage monitor and protections

47/64

Output voltage monitor and protections

L6713A monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP

and PGOOD (when applicable) conditions. The device shows different thresholds when

programming different operation mode (Intel or AMD, See Table 12) but the behavior in

response to a protection event is still the same as described below.

When using OFFSET functionality the OVP, UVP and PGOOD thresholds change in

according to the OFFSET voltage:

Protections are active also during soft-start (See “Soft-start” Section) while are masked

during D-VID transitions with an additional 32 clock cycle delay after the transition has

finished to avoid false triggering.

17.1

Under voltage

If the output voltage monitored by VSEN drops more than -750 mV below the programmed

reference for more than one clock period, L6713A turns OFF all MOSFETs and latches the

condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the

selected operative mode.

17.2

Preliminary over voltage

To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid

damage to the CPU in case of failed HS MOSFETs. In fact, since the device is supplied from

the 12 V bus, it is basically “blind” for any voltage below the turn-ON threshold (UVLOVCC).

In order to give full protection to the load, a preliminary-OVP protection is provided while

VCC is within UVLOVCC and UVLOOVP.

This protection turns-ON the low side MOSFETs as long as the VSEN pin voltage is greater

than 1.800 V with a 350 mV hysteresis. When set, the protection drives the LS MOSFET

with a gate-to-source voltage depending on the voltage applied to VCCDRx and

independently by the turn-ON threshold across these pins (UVLOVCCDR). This protection

depends also on the OUTEN pin status as detailed in Figure 22.

A simple way to provide protection to the output in all conditions when the device is OFF

(then avoiding the unprotected red region in Figure 22-Left) consists in supplying the

controller through the 5 VSB bus as shown in Figure 22-Right: 5 VSB is always present

before +12 V and, in case of HS short, the LS MOSFET is driven with 5 V assuring a reliable

protection of the load. Preliminary OVP is always active before UVLOVCC for both Intel and

AMD modes.

SEN

OUT

OFFSET

() I

OFFSET

()

OUT TH

[]

⇒

⋅

–

SEN TH

[]

OFFSET

() I

OFFSET

⋅

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