TDA7566

I2C Bus interface

19/28

5

Data transmission from microprocessor to the TDA7566 and viceversa takes place through

positive supply voltage must be connected).

5.1

Data Validity

As shown by Figure 25, the data on the SDA line must be stable during the high period of

the clock.

The HIGH and LOW state of the data line can only change when the clock signal on the SCL

line is LOW.

5.2

Start and Stop Conditions

As shown by Figure 26 a start condition is a HIGH to LOW transition of the SDA line while

SCL is HIGH.

The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.

5.3

Byte Format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an

acknowledge bit. The MSB is transferred first.

5.4

Acknowledge

The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock

pulse (see Figure 27). The receiver** the acknowledges has to pull-down (LOW) the SDA

line during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock

pulse.

* Transmitter

–

master (µP) when it writes an address to the TDA7566

–

slave (TDA7566) when the µP reads a data byte from TDA7566

** Receiver

–

slave (TDA7566) when the µP writes an address to the TDA7566

–

master (µP) when it reads a data byte from TDA7566

Figure 25.

SDA

SCL

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

D99AU1031