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March 2004

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HIGH SPEED:

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

WIDE OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 112

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SPACE GRADE-1: ESA SCC QUALIFIED

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50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

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NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

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DEVICE FULLY COMPLIANT WITH

SCC-9203-051

DESCRIPTION

The M54HC112 is an high speed CMOS DUAL

J-K FLIP-FLOP WITH PRESET AND CLEAR

The

M54HC112

dual

JK

flip-flop

features

individual J, K, clock, and asynchronous set and

clear inputs for each flip-flop. When the clock goes

high, the inputs are enabled and data will be

accepted. The logic level of the J and K inputs

may be allowed to change when the clock pulse is

high and the bistable will function as shown in the

truth table. Input data is transferred to the input on

the negative going edge of the clock pulse.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M54HC112

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

PIN CONNECTION

ORDER CODES

PACKAGE

FM

EM

DILC

M54HC112D

M54HC112D1

FPC

M54HC112K

M54HC112K1

DILC-16

FPC-16