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TDA7407 데이터시트(PDF) 18 Page - STMicroelectronics |
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TDA7407 데이터시트(HTML) 18 Page - STMicroelectronics |
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18 / 46 page ![]() Noise blanker part TDA7407 18/46 Figure 3. Vn timing diagram TS Suppression pulse duration (6) Signal HOLDN in testmode BLT = 00 TBD 38 TBD μs BLT = 10 TBD 32 TBD μs BLT = 01 TBD 25.5 TBD μs BLT = 00 TBD 22 TBD μs VRECTADJ Noise rectifier discharge adjustment (7) Signal PEAK in testmode NRD = 00 (5) (10) 0.3 (10) V/ms NRD = 01 (5) (10) 0.8 (10) V/ms NRD = 10 (5) (10) 1.3 (10) V/ms NRD = 11 (5) (10) 2.0 (10) V/ms SRPEAK Noise rectifier charge Signal PEAK in testmode PCH = 0 (8) (10) 10 (10) mV/ μs PCH = 1 (8) (10) 20 (10) mV/ μs VADJMP Noise rectifier adjustment through multipath (9) Signal PEAK in testmode MPNB = 00 (9) (10) 0.3 (10) V/ms MPNB = 01 (9) (10) 0.5 (10) V/ms MPNB = 10 (9) (10) 0.7 (10) V/ms MPNB = 11 (9) (10) 0.9 (10) V/ms 1. All Thresholds are measured using a pulse with TR =2ms, THIGH = 2ms and TF = 10ms. The repetition rate must not increase the PEAK voltage 2. NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold 3. NAT represents the Noiseblanker Byte bit pair D4, D3 for the noise controlled triggeradjustment 4. OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector 5. FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control 6. BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment 7. NRD represents the Configuration Byte bit pair D1, D0 for the noise rectifier discharge adjustment 8. PCH represents the Stereo decoder Byte bit D5 for the noise rectifier charge current adjustment 9. MPNB represents the HighCut Byte bit D7 and the Fieldstrength Byte D7 for the noise rectifier multipath adjustment 10. By design / characterization functionally guaranteed through dedicated test mode structure Table 7. Noise blanker electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit VOP VIN DC TR THIGH TF Time D97AU636 |
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