PM6675AS datasheet(43/48 Pages) STMICROELECTRONICS

43 / 48 page

PM6675AS

Application information

43/48

where k is a free design parameter greater than unity (k > 3) . It determinates the minimum

integrator capacitor value CINT:

Equation 49

If the ripple on pin COMP is greater than the integrator output dynamic (150 mV), an

additional capacitor Cfilt could be added in order to reduce its amplitude. If q is the desired

attenuation factor of the output ripple, select:

Equation 50

In order to reduce noise on pin COMP, it’s possible to introduce a resistor RINT that, together

with CINT and Cfilt, realizes a low pass filter. The cutoff frequency must be much greater (10

or more times) than the switching frequency of the section:

Equation 51

For most of applications both RINT and Cfilt are unnecessary.

If the ripple is very small (e.g. such as with ceramic capacitors), a further compensation

network, called “Virtual ESR” network, is needed. This additional part generates a triangular

ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is

represented in Figure 40.

Figure 40.

Virtual ESR network

Vref

Zout

INT

⋅

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

⋅

)

(

INT

filt

−

⋅

FILT

INT

FILT

INT

CUT

INT

⋅

VREF

CFILT

CINT

RINT

PWM Comparator

0.6V

VOUT

Ton

Generation

Block

Integrator

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