PM6675STR datasheet(24/53 Pages) STMICROELECTRONICS

24 / 53 page

Device description

PM6675S

24/53

Figure 35.

Circuitry for output ripple compensation

The additional capacitor is used to reduce the voltage on the COMP pin when higher than

300 mVpp and is unnecessary for most of applications. The trans conductance amplifier

(gm) generates a current, proportional to the DC error, used to charge the CINT capacitor.

The voltage across the CINT capacitor feeds the negative input of the PWM comparator,

forcing the loop to compensate the total static error. An internal voltage clamp forces the

COMP pin voltage range to ±150 mV respect to VREF. This is useful to avoid or smooth

output voltage overshoot during a load transient. When the Pulse-Skip Mode is entered, the

clamping range is automatically reduced to 60 mV in order to enhance the recovering

capability. If the ripple amplitude is larger than 150 mV, an additional capacitor CFILT can be

connected between the COMP pin and ground to reduce ripple amplitude, otherwise the

integrator will operate out of its linearity range. This capacitor is unnecessary for most of

applications and can be omitted.

The design of the external feedback network depends on the output voltage ripple. If the

ripple is higher than approximately 20 mV, the correct CINT capacitor is usually enough to

keep the loop stable. The stability of the system depends firstly on the output capacitor zero

frequency.

The following condition must be satisfied:

Equation 6

where k is a fixed design parameter (k > 3). It determinates the minimum integrator

capacitor value:

VREF

REF

COMP

VSNS

RFb1

Fb1

RFb2

Fb2

PWM

Comparator

CINT

INT

RINT

INT

CFILT

FILT

COUT

OUT

COMP PIN

VOLTAGE

OUTPUT

VOLTAGE

I=gm(V1-Vr)

V11

∆V

CINT

INT

ESR

out

Zout

⋅

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