PM6685 datasheet(40/52 Pages) STMICROELECTRONICS

40 / 52 page

Monitoring and protections

PM6685

40/52

Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple.

If the ripple is very small (lower than approximately 30mV), a further compensation network,

named virtual ESR network, is needed. This additional part generates a triangular ripple

that is added to the ESR output voltage ripple at the input of the integrator network. The

complete control schematic is represented in Figure 37.

Figure 37. Virtual ESR network

The T node voltage is the sum of the output voltage and the triangular waveform generated

by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent

ESR RESR.

A good trade-off is to design the network in order to achieve an RESR given by:

Equation 26

where

∆IL is the inductor current ripple and VRIPPLE is the overall ripple of the T node

voltage. It should be chosen higher than approximately 30mV.

The stability of the system depends firstly on the output capacitor value and on RTOT:

Vrr

arra

atto

orr

CIINNTT

RIINNTT

CFFIILLTT

COOUUTT

COMP PIN

VOLTAGE

OUTPUT

VOLTAGE

I=gm(V1-Vr)

T NODE

VOLTAGE

∆V

∆V1

ROOUUTT

∆V1

out

RIPPLE

ESR

−

∆

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