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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LFEC10 데이터시트(PDF) 28 Page - Lattice Semiconductor |
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LFEC10 데이터시트(HTML) 28 Page - Lattice Semiconductor |
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28 / 163 page  2-25 Architecture Lattice Semiconductor LatticeECP/EC Family Data Sheet Figure 2-29. Output Register Block Figure 2-30. ODDRXB Primitive Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block. In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D- type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). D Q D Q D-Type ONEG0 From Routing CLK1 Programmed Control DO Latch LE* *Latch is transparent when input is low. OPOS0 OUTDDN /LATCH 0 1 0 1 To sysIO Buffer ODDRXB LSR Q DB CLK DA |
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