ADE3800_05 datasheet(24/138 Pages) STMICROELECTRONICS

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ADE3800

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The ideal ADC clamp signal would be greater than 1us wide and placed precisely between the SOG

pulse and video data. Any overlap or misalignment will alter the Green offset level internally and

comparators may lose track of SOG signal.

Level Adjustment

All 3 comparator thresholds and clamp voltage are moved up or down together by changing

registers. These cannot be individually adjusted.

● To shift up:

— Set ANA_ADC_SOG_1[7:4] = 0F

— Adjust ANA_ADC_SOG_0[4:0] to a higher value. (The default is 0, ~8.8mV per increment.)

● To shift down:

— Set ANA_ADC_SOG_0[4:0] = 0b00000

— Adjust ANA_ADC_SOG_1[7:4] to a lower value. (The default is 0F, ~10mV per decrement; a

value of 00 is invalid.)

To power down SOG, set ANA_ADC_SOG_1[0] = 1.

Note:

The SMEAS block can still detect SOG activity while the ADC is powered down.

There are three SOG analog voltage comparators that generate the SOG0, SOG1, and SOG2

digital signals. These signals are then sent to the LLK, SRT, SMEAS, and SMUX blocks.

For SOG support the SMEAS block has:

● Three 8-bit edge counters (used to detect activity)

● Four 4-bit delay counters (used to tune the comparator reference voltages)

Figure 5: SOG Lock Phase

SOG output waveform has the same polarity as input

ADCSOG1[0] = 0 (pwdnSOG)

ADCSOG1[3] (enSOG) = ADCGRN2[1] = 0

Clamp Position

ADE3800 데이터시트(PDF) 24 Page - STMicroelectronics