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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADE3800 데이터시트(PDF) 35 Page - STMicroelectronics |
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ADE3800 데이터시트(HTML) 35 Page - STMicroelectronics |
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35 / 138 page  35/138 ADE3800 Register Description by Block Note: All thresholds are in XCLK units. SRT_VS_SEL 01EF [5:4] 00 sclk div prescaler for SMEAS: 0*: 128 1: 256 2: 512 3: 1024 R [3] Bad csync threshold. Change SRT_CSYNC_THR until this is stable low. R/W [2:0] vert sync source select for re-sampling into inclk domain for SMUX: 0*: VSYNC pin 1: vsync from composite HSYNC pin 2: vsync from composite SOG[0] comparator 3: vsync from composite SOG[1] comparator 4: vsync from composite SOG[2] comparator 5: filtered and delayed vsync (normal) 6: vsync from alt SOG source pin 7: reserved SRT_COAST_RISE_HW_L SRT_COAST_RISE_HW_M SRT_COAST_RISE_HW_U 01F0 01F1 01F2 R R R [7:0] [7:0] [7:0] Shadow read back SRT_COAST_FALL_HW_L SRT_COAST_FALL_HW_M SRT_COAST_FALL_HW_U 01F3 01F4 01F5 R R R [7:0] [7:0] [7:0] Table 16: Sync Retiming Registers (Sheet 2 of 2) Register Name Addr Mode Bits Rst Description |
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