ADE3800XL datasheet(20/138 Pages) STMICROELECTRONICS

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ADE3800

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4.2

Frequency Synthesizer (FSYN)

The Frequency Synthesizer block generates the output clock, the dot clock and the scaler clock

(SCLK). Frequency modulation, phase control, and pulse extension (duty cycle control) of the

output clock are also provided.

For consistency and ease of use, both clocks are programmed by means of a single-parameter –

the phase rate value derived from the desired frequency.

4.2.1

Dotclock vs Outclock

Dot clock (also known as DOTCLK or DCLK) is an internal clock; there are no associated I2C

registers.

Out clock is the pixel clock that drives the LCD panel:

● When driving 2 pixels per clock, out clock and dot clock are identical

● When driving 1 pixel per clock the out clock frequency is half the dot clock frequency (phase

rate is proportional to clock period which is the inverse of frequency).

Refer to Table 12: Clock Relationship.

GLBL_AZWC_CTRL

000F

R/W

[7:2]

Reserved

[1]

Auto Zero Window Control and Clamp synchronization

0: Synchronization on INCLK

1: Synchronization on DOTCLK

[0]

Reserved

DFT_DEL_REF

0F0B

[7:0]

Returns chip speed and gate propagation delay (number of

gates propagation per XCLK period)

a. Refer to OMUX_CTRL0[0] and also to Table 12.

b. Refer to OMUX_CTRL0[0] and also to Table 12.

c. If set, this bit puts the SDA output in push-pull mode (instead of open drain) to achieve higher I²C speed.

d. If reset, the device is put in shutdown mode (lowest possible power consumption) but can only exit from that

mode with an external reset or a power on/off.

Table 10: FSYN Frequency Synthesizer Registers (Sheet 1 of 2)

Addr

Mode

Bits

Rst

Description

FSYN_CTRL

0850

R/W

[0]

frequency modulation

0*: off

1: on

FSYN_PR_OTCLK_0

FSYN_PR_OTCLK_1

FSYN_PR_OTCLK_2

0851

0852

0853

R/W

[7:0]

[5:0]

output clock phase rate

= 2^21 * XCLK_FREQ / OUT_CLK_FREQ

FSYN_OFFSET

0854

R/W

[7:0]

RSDS clock-data skewcontrol (no meaning in LVDS)

LSB = 289ps

Table 9: Global Control Registers (Sheet 3 of 3)

Addr

Mode

Bits

Rst

Description

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