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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADE3800XT 데이터시트(PDF) 54 Page - STMicroelectronics |
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ADE3800XT 데이터시트(HTML) 54 Page - STMicroelectronics |
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54 / 138 page  Register Description by Block ADE3800 54/138 ● Background color management For formulae to program the registers refer to Chapter 7: Scaler Equations on page 132. 4.10.1 Frame Synchronization Due to the limited pixel memory of the chip, the output active video needs to be perfectly synchronized with the input active video. This mode of operation is called Frame Lock. Figure 9: Frame Lock Operation Table 23: Scale Registers (Sheet 1 of 3) Register Name Addr R/W Bits Rst Description SCL_SRC_HPIX_L SCL_SRC_HPIX_U 0A00 0A01 R/W R/W [7:0] [3:0] 00 00 input horizontal resolution SCL_SRC_VPIX_L SCL_SRC_VPIX_U 0A02 0A03 R/W R/W [7:0] [3:0] 00 00 input vertical resolution SCL_SCALEFACH_L SCL_SCALEFACH_M SCL_SCALEFACH_U 0A04 0A05 0A06 R/W R/W R/W [7:0] [7:0] [0] 00 00 00 17-bit horizontal scale factor SCL_SCALEFACV_L SCL_SCALEFACV_M SCL_SCALEFACV_U 0A07 0A08 0A09 R/W R/W R/W [7:0] [7:0] [0] 00 00 00 17-bit vertical scale factor SCL_ORIGHPOS_L SCL_ORIGHPOS_U 0A0A 0A0B R/W R/W [7:0] [7:0] 00 00 2’s complement , signed number 27-bit horizontal position of the first output pixel SCL_ORIGVPOS_L SCL_ORIGVPOS_U 0A0C 0A0D R/W R/W [7:0] [7:0] 00 00 2’s complement , signed number 27-bit vertical position of the first output pixel SCL_PIPE_RATE_L SCL_PIPE_RATE_U 0A0E 0A0F R/W R/W [7:0] [3:0] 00 00 Programmable update rate, which controls when a new pixel column is read out of the line buffer. For (sclk==dotclk) && (dest_hpix == in_hpix), pipe_rate = 0. |
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