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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADE3800SXL 데이터시트(PDF) 97 Page - STMicroelectronics |
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ADE3800SXL 데이터시트(HTML) 97 Page - STMicroelectronics |
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97 / 138 page  97/138 ADE3800 Register Description by Block The split line buffer can delay and re-interleave the input pixel stream so that a 2 ppc output can drive both the first and the half line pixels simultaneously. This is commonly used for TCON applications where the column drivers are split into two groups (left and right halves of the screen) and driven at ½ the pixel rate. Control signals need to be similarly delayed in the TCON to account for the ½ line temporal shift. Latency is not important as long as the timing relationship between HSync, vsync, enable and data is preserved at the output. Figure 20: Mux block diagram 8 right shift 8 byte flip red & blue swap 8 8 right shift 8 byte flip 8 8 right shift 8 byte flip 8 rin[7:0] gin[7:0] bin[7:0] 24 single to double wide converter & RSDS data pair iinversion 48 hclk enab_in hsync_in vsync_in tcon_in[7:0] LVDS data swap & inversion RSDS data pair function 24 FLOPS 14 8 tcon_out [7:0] 56 6 lvds_out [55:0] 24 tci[13:0] F L O P S lvds_clk_out rsds_clka_out rsds_clkb_out pwm _a_in pwm _b_in 2 dotclk dotclkx2 (otclk) 56 rsds_out [23:0] |
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