STE2002_06 datasheet(49/61 Pages) STMICROELECTRONICS

49 / 61 page

STE2002

Electrical characteristics

49/61

Serial interface (

Figure 51)

TCYC

Clock Cycle SCLK

VDD1 = 1.7V; Write

(2) (5)

150

TPWH1

SCLK pulse width HIGH

TPWL1

SCLK Pulse width LOW

TS2

SCE setup time

TH2

SCE hold time

TPWH2

SCE minimum high time

TS3

SD/C setup time

TH3

SD/C hold time

TS4

SDIN setup time

TH4

SDIN hold time

TS5

SOUT Access Time

100

TH5

SOUT Disable Time vs.

SCLK

100

TH6

SOUT Disable Time vs.

SCE

100

All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and

VIH with an input voltage swing of VSS to VDD

Cb is the capacitive load for each bus line.

For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

CVLCD is the filtering Capacitor on VLCDOUTTrise and Tfall (30%-70%) = 10 ns

Table 27.

AC operation (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

frame

960

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