STE2007_06 datasheet(13/62 Pages) STMICROELECTRONICS

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STE2007

Electrical characteristics

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3.5

Driver TxData mode

Note:

Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is always 3-8ns

before SCLK pulse falling edge

The input signal rise and fall times must be within 10ns.

Every timing is specified on the basis of 30% and 70% of VDDI.

Note:

The input signal rise and fall times must be within 10ns.

Every timing is specified on the basis of 30% and 70% of VDDI.

Table 11.

Input signals change time

Signal

Symbol

Parameter

Min.

Typ.

Max.

Unit

Inputs

tr,tf

(1)

To 30% & 70% levels

Table 12.

Timings based on 4 MHz SCLK speed

Symbol

Item

Condition

Min.

Typ.

Max.

Units

Data hold time

Note 1

100

125

Access time

–

100

Output disable time

–

100

Data setup time

–

100

–

!CS pulse width high

–

250

Table 13.

Timings based on 1 MHz SCLK speed

Symbol

Item

Condition

Min.

Typ.

Max.

Units

Data hold time

–

100

125

Access time

–

450

Output disable time

–

450

Data setup time

–

100

–

1CS pulse width high

–

250

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