Architectural features and block diagram

STLS2E02

2/5

1

Architectural features and block diagram

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CPU

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Out-of-order superscalar 64bit architecture

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MIPS based

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9 stage pipeline organized in fetch, pre-decode, decode, reg-map, dispatch, issue,

reg-read,execution and commit

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Up to 64 instructions executed out-of-order with four issue mechanism

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64bit register file (32 fix+32 float)

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Register renaming unit composed by 64-entry physical register files

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Branch prediction unit

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Six functional units: two integer, two float, one SIMD unit, one load/store unit

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Memory Hierarchy

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64KB + 64KB four-ways set-associative first level instruction and data cache

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512KB four-ways set associative unified second level cache

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Up to 24 non-blocking accesses with on-the-fly Memory Disambiguation

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Load speculation through value return from previous pending stores

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Miss word first access for cache miss access

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Instruction 16-entry TLB (Table Lookside Buffer) and unified 64-entry TLB with

page size from 4KB to 4MB

Figure 1.

Block diagram

L2 cache

DDR

DDR

Controller

Cache Interface

Writeback

Queue

Miss

Queue

Refill Bus

Branch Bus

BTB

BHT

BRQ

Fix

RS

Float

RS

Integer

Register

File

Floating

Point

Register

File

Map Bus

ROQ

ALU1

ALU2

AGU

FPU1

TLB

CP0

Queue

D-Cache

64KB

FPU2

ITLB

I-Cache

64KB

Commit Bus

Writeback Bus

Reorder Queue

Arbitrator

SysAD

SysAD64

Controller

AC00116