STPC4EDBI datasheet(75/93 Pages) STMICROELECTRONICS

75 / 93 page

DESIGN GUIDELINES

Release 1.5 - January 29, 2002

75/93

6.3.10. TV INTERFACE

The STPC integrates a voltage reference and

video DACs. The amount of external devices is

then limited to video buffers as described in the

Figure 6-15.

The connection from IREFx and VREFx up to the

20 ohms resistors must be as short as possible.

The constraint is the same for the connection from

VDDA_TV and VSSA_TV up to the decoupling

capacitances.

The resistors and capacitors of the amplifier stage

have to be as close as possible to the video buffer.

When the TV interface is not needed, the signals

RED, GREEN, BLUE, CVBS, IREF1, IREF2 can

be left unconnected, VDDA_TV must then be

connected to GND.

R,G,B,CVBS outputs:

. Ioutmax = 80.704 / Rref < 5mA

. Rload = 274 ohms

. Vout = {10-bit code} x Rload x 0.079 / Rref

Fine tuning of the maximum output level must be

done using the gain control registers 0x11 to 0x13

of the integrated Digital Encoder (write the value

0x0B for a gain of 109%).

Figure 6-15. Typical VGA implementation

20 1%

IREF1

VREF1

IREF2

VREF2

VDDA_TV

2.5V

10nF

100nF 22uF

DCLK

CVBS

RED

GREEN

BLUE

316 1%

27MHz

47pF

FBEAD

VSSA_TV

AGND

GND

3.3V

FBEAD

100nF

GND

same

as for

RED

AGND

15uH

AGND

526

326

478 1%

AGND

VCCA

To the connector

75 1%

TSH74

100nF 22uF

FBEAD

AGND

FBEAD

GND

VCCA

GND

Rref = 20K 1%

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