M24C02WDW6TP datasheet(9/34 Pages) STMICROELECTRONICS

9 / 34 page

M24C16, M24C08, M24C04, M24C02, M24C01

Signal description

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2.4

Supply voltage (VCC)

2.4.1

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 6, Table 7 and

Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the

VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the

VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

2.4.2

Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC; the VCC rise time must not

vary faster than 1 V/µs.

2.4.3

Device reset

In order to prevent inadvertent write operations during power-up, a power on reset (POR)

circuit is included. At power-up (continuous rise of VCC), the device does not respond to any

instruction until VCC has reached the power on reset threshold voltage (this threshold is

lower than the minimum VCC operating voltage defined in Table 6, Table 7 and Table 8).

When VCC passes the POR threshold, the device is reset and in the Standby Power mode.

In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops

below the power on reset threshold voltage, the device stops responding to any instruction

sent to it.

2.4.4

Power-down conditions

During power-down (where VCC decreases continuously), the device must be in the Standby

Power mode (mode reached after decoding a Stop condition, assuming that there is no

internal write cycle in progress).

Figure 4.

Maximum RP value versus bus parasitic capacitance (C) for an I²C bus

AI01665b

VCC

SDA

MASTER

SCL

100

C (pF)

1000

fc = 400kHz

fc = 100kHz

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