M24C16, M24C08, M24C04, M24C02, M24C01

Device operation

13/34

Figure 6.

Write mode sequences with WC = 1 (data write inhibited)

3.6

Write operations

Following a Start condition the bus master sends a device select code with the Read/Write

bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for an

address byte. The device responds to the address byte with an acknowledge bit, and then

waits for the data byte.

bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is

triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.

During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and

the device does not respond to any requests.

3.6.1

Byte Write

After the device select code and the address byte, the bus master sends one data byte. If

the addressed location is Write-protected, by Write Control (WC) being driven High (during

the period from the Start condition until the end of the address byte), the device replies to

the data byte with NoAck, as shown in Figure 6, and the location is not modified. If, instead,

the addressed location is not Write-protected, the device replies with Ack. The bus master

terminates the transfer by generating a Stop condition, as shown in Figure 7.

Byte Write

DEV SEL

BYTE ADDR

DATA IN

WC

Page Write

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

WC

DATA IN 3

AI02803C

Page Write

(cont'd)

WC (cont'd)

DATA IN N

ACK

ACK

NO ACK

R/W

ACK

ACK

NO ACK

NO ACK

R/W

NO ACK

NO ACK