MSC7118 datasheet(49/60 Pages) FREESCALE

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Hardware Design Considerations

MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7

Freescale Semiconductor

3.3.6

Example Total Power Consumption

Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is

estimated as the following:

PTOTAL = 324.0 + (4 × 4.32) + 326.3 + (10 × 5.44) + 64 = 784.98 mW

Eqn. 13

3.4

Reset and Boot

This section describes the recommendations for configuring the MSC7118 at reset and boot.

3.4.1

Reset Circuit

HRESET

is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For

an open-drain output such as HRESET, take care when driving many buffers that implement input bus-hold circuitry. The

bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller

value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7118 output

current, the pull-up value should not be too small (a 1 K

Ω pull-up resistor is used in the MSC711xADS reference design).

3.4.2

Reset Configuration Pins

Table 30 shows the MSC7118 reset configuration signals. These signals are sampled at the deassertion (rising edge) of

PORESET

. For details, refer to the Reset chapter of the MSC711x Reference Manual.

Table 30. Reset Configuration Signals

Signal

Description

Settings

BM[3–0]

Determines boot mode.

See Table 31 for details.

SWTE

Determines watchdog functionality.

Watchdog timer disabled.

Watchdog timer enabled.

HDSP

Configures HDI16 strobe polarity.

Host Data strobes active low.

Host Data strobes active high.

H8BIT

Configures HDI16 operation mode.

HDI16 port configured for 16-bit operation.

HDI16 port configured for 8-bit operation.

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