HD151TS307ARP

Rev.4.00 Jul. 08, 2004 page 4 of 8

DC Electrical Characteristics / SSC Clock Output

Ta = 0 to 70°C, VDD = 3.3 V±5%

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

3.1

—

—

V

Output voltage

——

50

mV

—

–30

—

Output current *

1

—30

—

mA

Note:

1. Parameters are target of design. Not 100% tested in production.

AC Electrical Characteristics / SSC Clock Output

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

Notes

—

| 250 |

| 300 |

SSCCLKOUT, 24 MHz

—

| 250 |

| 300 |

SSCCLKOUT, 48 MHz

SSCOFF

SEL1:0 = 10

Fig1

—

| 250 |

| 300 |

SSCCLKOUT, 24 MHz

—

| 250 |

| 300 |

SSCCLKOUT, 48 MHz

SSC=

±0.25%

SEL1:0 = 11

Fig1

—

| 250 |

| 300 |

SSCCLKOUT, 24 MHz

Cycle to cycle jitter

*1, 2

—

| 250 |

| 300 |

ps

SSCCLKOUT, 48 MHz

SSC=

±1.5%

SEL1:0 = 01

Fig1

23.8

—

24.2

SSCCLKOUT,

XIN = 24 MHz

47.3

—

48.7

SSCCLKOUT,

XIN = 48 MHz

SSCOFF

SEL1:0 = 10

23.7

—

24.3

SSCCLKOUT,

XIN = 24 MHz

47.2

—

48.8

SSCCLKOUT,

XIN = 48 MHz

SSC=

±0.25%

SEL1:0 = 11

23.4

—

24.6

SSCCLKOUT,

XIN = 24 MHz

Output frequency

*1, 2

46.6

—

49.4

MHz

SSCCLKOUT,

XIN = 48 MHz

SSC=

±1.5%

SEL1:0 = 01

Slew rate

*1

0.8

—

—

V/ns

@48 MHz

0.4 V to 2.4 V

Clock duty cycle

*1

45

50

55

%

Output impedance

*1

—40

—

Ω

Spread spectrum

modulation frequency

*1

—

33

—

KHz

@48 MHz, SSCCLKOUT

Input clock frequency

10

—

60

MHz

Stabilization time

*1,3

——

2

ms

Notes: 1. Parameters are target of design. Not 100% tested in production.

2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.

3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after

power up.