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HD74LVC125ATELL 데이터시트(PDF) 1 Page - Renesas Technology Corp

부품명 HD74LVC125ATELL
상세설명  Quad. Bus Buffer Gates with 3-state Outputs
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
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Rev.4.00 Jul. 23, 2004 page 1 of 6
HD74LVC125A
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0348–0400Z
(Previous ADE-205-108C (Z))
Rev.4.00
Jul. 23, 2004
Description
The HD74LVC125A has four bus buffer gates in a 14 pin package. The device require the three state control input C to
be taken high to put the output into the high impedance condition, whereas the device requires the control input to be
low to put the output into high impedance. Low voltage and high-speed operation is suitable at the battery drive
product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
• V
CC = 2.0 V to 5.5 V
• All inputs V
IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs V
OUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
• Typical V
OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical V
OH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@V
CC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LVC125AFPEL
SOP–14 pin (JEITA)
FP–14DAV
FP
EL (2,000 pcs/reel)
HD74LVC125ATELL
TSSOP–14 pin
TTP–14DV
T
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
CA
Outputs Y
HX
Z
LLL
LH
H
H:
High level
L:
Low level
X:
Immaterial
Z:
High impedance


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