HD74LV1GW98ACME datasheet(3/9 Pages) RENESAS

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HD74LV1GW98A

Rev.3.00, May 19, 2006 page 3 of 8

Function Selection Table

Logic Function

Figure No.

2 to 1 data Selector

2–inputs NAND

2–inputs NOR with one input inverted

2–inputs AND with one input inverted

2–inputs NAND with one input inverted

2–inputs OR with one input inverted

2–inputs NOR

Non–Invert Buffer

Inverter

Logic Configurations

Figure 1. 2 to 1 Data Selector

1 (IN1)

(IN2) 6

2 (GND) (VCC) 5

3 (IN0)

(Y) 4

A/B

VCC

A/B

Figure 2. 2–inputs NAND Gate

1 (IN1)

(IN2) 6

2 (GND) (VCC) 5

3 (IN0)

(Y) 4

VCC

Figure 3. 2–inputs NOR Gate

with A input inverted

1 (IN1)

(IN2) 6

2 (GND) (VCC) 5

3 (IN0)

(Y) 4

VCC

Figure 4. 2–inputs NAND Gate

with A input inverted

1 (IN1)

(IN2) 6

2 (GND) (VCC) 5

3 (IN0)

(Y) 4

VCC

1 (IN1)

(IN2) 6

2 (GND) (VCC) 5

3 (IN0)

(Y) 4

VCC

Figure 5. 2–inputs NOR Gate

1 (IN1)

(IN2) 6

2 (GND) (VCC) 5

3 (IN0)

(Y) 4

VCC

Figure 6. Non–Invert Buffer

1 (IN1)

(IN2) 6

2 (GND) (VCC) 5

3 (IN0)

(Y) 4

VCC

Figure 7. Inverter

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