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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD74LS195AFPEL 데이터시트(PDF) 6 Page - Renesas Technology Corp |
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HD74LS195AFPEL 데이터시트(HTML) 6 Page - Renesas Technology Corp |
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6 / 8 page  HD74LS195A Rev.3.00, Jul.15.2005, page 6 of 7 Waveform Clear Clock Data Shift/Load Outputs Q 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V tTLH tTLH tTHL tPHL tPLH tPHL tsu tsu tsu tsu tsu tn th trelease trelease th tn tn+1 tn+1 tTHL tw (CLR) VOH VOL 0V 3V 0V 3V 0V 3V 0V 3V 10% 10% 10% 10% 90% 90% 90% 90% tw (CK) Notes: 1. Input pulse; tTLH ≤ 15 ns, t THL ≤ 6 ns, PRR = 1 MHz, duty cycle 50% 2. A clear pulse is applied prior to each test. 3. Propagation delay times (tPLH and tPHL) are measured at tn + 1. Proper shifting of data is verified at tn + 4 with a functional test. 4. J and K inputs are tested the same as data A, B, C, and D inputs except that shift / load input remains high. 5. tn; bit time beroer clocking transition. 6. tn + 1; bit time after one clocking transition. 7. tn + 4; bit time after four clocking transition. |
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