32C80 datasheet(12/60 Pages) RENESAS

12 / 60 page

Page 12

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers.

The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers.

Two sets of register banks are provided.

Figure 2.1 CPU Register

b23

R0H

R0L

R1H

R1L

b31

USP

ISP

INTB

High-speed Interrupt Registers

b15

b23

SVF

SVP

VCT

DMAC-associated Registers

b23

DMD0

DCT0

DCT1

b15

DRC0

DRC1

DMA0

DMA1

DMD1

DRA0

DRA1

Data Register(1)

Address Register(1)

Static Base Register(1)

Frame Base Register(1)

User Stack Pointer

Interrupt Stack Pointer

Interrupt Table Register

Program Counter

Flag Save Register

PC Save Register

Vector Register

DMA Mode Register

DMA Transfer Count Register

DMA Transfer Count Reload Register

DMA Memory Address Register

DMA SFR Address Register

DMA Memory Address Reload Register

NOTE:

1. The register bank is comprised of these registers. Two sets of register banks are provided.

General Registers

b15

Carry Flag

Debug Flag

Zero Flag

Sign Flag

Overflow Flag

Interrupt Enable Flag

Stack Pointer Select Flag

Reserved Space

Processor Interrupt Priority Level

Reserved Space

FLG

Flag Register

IPL

U I O B S Z D C

DSA0

DSA1

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