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4282 데이터시트(PDF) 29 Page - Renesas Technology Corp

부품명 4282
상세설명  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  69 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4282 데이터시트(HTML) 29 Page - Renesas Technology Corp

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Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Rev.1.33
Mar 18, 2004
page 29 of 67
4282 Group
BML p, a (Branch and Mark Long to address a in page p)
00111p3
p2
p1
p0
07p
22
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note:
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
Operation:
(SK(SP))
← (PC)
(SP)
← (SP) + 1
(PCH)
← p
(PCL)
← a6–a0
BMLA p, a (Branch and Mark Long to address a in page p)
001010000
050
22
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (a6 a5 a4 A3 A2 A1 A0) determined
by replacing the low-order 4 bits of address
a in page p with register A.
Note:
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
CCK (Change system Clock to f(XIN))
001011001
059
11
–
–
Grouping:
Other operation
Description: Changes system clock (STCK) from f(XIN)/8
to f(XIN). Execute this instruction at address
0 in page 0.
Operation:
Change to STCK = f(XIN)
2
16
10a6
a5
a4
a3
a2
a1
a0
1aa
Operation:
(SK(SP))
← (PC)
(SP)
← (SP) + 1
(PCH)
← p
(PCL)
← (a6–a4, A3–A0)
2
16
10a6
a5
a4
p3
p2
p1
p0
1ap
CLD (CLear port D)
000010001
011
11
–
–
Grouping:
Input/Output operation
Description: Clears (0) to port D (high-impedance state).
Operation:
(D)
← 1



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