M38264EBFS datasheet(52/91 Pages) RENESAS

52 / 91 page

Rev.1.00

Sep 06, 2006

page 52 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

Fig. 56 Example of reset circuit

RESET CIRCUIT

When the power source voltage is within limits, and main clock

XIN-XOUT is stable, or a stabilized clock is input to the XIN pin, if

the RESET pin is held at an “L” level for 2 µs or more, the micro-

computer is in an internal reset state. Then the RESET pin is

returned to an “H” level, reset is released after approximate 8200

cycles of f(XIN), the program in address FFFD16 (high-order byte)

Fig. 57 Reset Sequence

and address FFFC16 (low-order byte). Make sure that the reset in-

put voltage is less than 0.2 VCC(min.) for the power source voltage

of VCC(min.).

*VCC(min.) = Minimum value of power supply voltage limits

applied to VCC pin

VCC

RESET

VCC

RESET

Power source

voltage detection

circuit

VCC

RESET

Power on

0.2VCC level

Oscillation stabilized

2 µs

XIN

(Note)

Note: Reset release voltage Vcc = Vcc (min.)

ADL

FFFC

FFFD

ADH,

Undefined

XIN : Approx. 8200 cycles

Note : The frequency of system clock φ is f(XIN) divided by 8.

Reset address from

vector table

RESET

Internal reset

Address

Data

SYNC

System

clock φ

XIN

ADH

ADL

UndefinedUndefined

Undefined

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