7547 datasheet(8/91 Pages) RENESAS

8 / 91 page

7547 Group

Rev.1.21

Nov 15, 2006

page 8 of 89

REJ03B0156-0121

Execute JSR

On-going Routine

M (S)

(PCH)

(S)

(S – 1)

M (S)

(PCL)

Execute RTS

(PCL)

M (S)

(S)

(S – 1)

(S)

(S + 1)

(S)

(S + 1)

(PCH)

M (S)

Subroutine

Restore Return

Address

Store Return Address

on Stack

M (S)

(PS)

Execute RTI

(PS)

M (S)

(S)

(S – 1)

(S)

(S + 1)

Interrupt

Service Routine

Restore Contents of

Processor Status Register

M (S)

(PCH)

(S)

(S – 1)

M (S)

(PCL)

(S)

(S – 1)

(PCL)

M (S)

(S)

(S + 1)

(S)

(S + 1)

(PCH)

M (S)

Restore Return

Address

I Flag “0” to “1”

Fetch the Jump Vector

Store Return Address

on Stack

Store Contents of Processor

Status Register on Stack

Interrupt request

(Note)

Note : The condition to enable the interrupt

Interrupt enable bit is “1”

Interrupt disable flag is “0”

Table 4 Push and pop instructions of accumulator or processor status register

Accumulator

Processor status register

Push instruction to stack

PHA

PHP

Pop instruction from stack

PLA

PLP

Fig. 5 Register push and pop at interrupt generation and subroutine call

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