Rev.2.00, Oct 06, 2005 page 1 of 6

HD74HC78

Dual J-K Flip-Flops

(with Preset, Common Clear and Common Clock)

REJ03D0553-0200

(Previous ADE-205-425)

Rev.2.00

Oct 06, 2005

Description

This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each

flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear

and a common clock. Preset and clear are independent of the clock and accomplished by a low logic level on the

corresponding input.

Features

• High Speed Operation: t

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: I

µA max (Ta = 25°C)

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74HC78FPEL

SOP-14 pin (JEITA)

PRSP0014DF-B

(FP-14DAV)

FP

EL (2,000 pcs/reel)

HD74HC78RPEL

SOP-14 pin (JEDEC)

PRSP0014DE-A

(FP-14DNV)

RP

EL (2,500 pcs/reel)

Note:

Please consult the sales office for the above package availability.

Function Table

Inputs

Outputs

Preset

Clear

Clock

J

K

Q

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

L

X

X

X

H

*1

H

*1

H

H

L

L

No change

H

H

L

H

L

H

H

H

H

L

H

L

H

H

H

H

Toggle

H

H

L

X

X

No change

H

H

H

X

X

No change

H

H

X

X

No change

H :

High level

L :

Low level

X :

Irrelevant

Note:

1. Q and

Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and

Clear go High simultaneously.