HD74AC374/HD74ACT374

Rev.2.00, Jul.16.2004, page 2 of 9

Pin Arrangement

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

OE

Gnd

CP

(Top view)

Logic Symbol

CP

OE

Pin Names

D

Data Inputs

CP

Clock Pulse Input

OE

3-State Output Enable Input

O

3-State Outputs

Functional Description

The HD74AC374/HD74ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state

true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will

store the state of their individual D inputs that meet the setup and hold time requirements on the Low-to-High Clock

(CP) transition. With the Output Enable (

OE) Low, the contents of the eight flip-flops are available at the outputs.

When the

OE is High, the outputs go to the high impedance state. Operation of the OE input does not affect the state of

the flip-flops.