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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7145 데이터시트(PDF) 73 Page - Renesas Technology Corp |
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SH7145 데이터시트(HTML) 73 Page - Renesas Technology Corp |
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73 / 930 page  2. CPU Rev.4.00 Mar. 27, 2008 Page 29 of 882 REJ09B0108-0400 2.4.3 Instruction Format The instruction formats and the meaning of source and destination operand are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement Table 2.9 Instruction Formats Instruction Formats Source Operand Destination Operand Example 0 format xxxx xxxx xxxx xxxx 15 0 — — NOP — nnnn: Direct register MOVT Rn Control register or system register nnnn: Direct register STS MACH,Rn n format xxxx xxxx xxxx nnnn 15 0 Control register or system register nnnn: Indirect pre- decrement register STC.L SR,@-Rn mmmm: Direct register Control register or system register LDC Rm,SR m format xxxx mmmm xxxx xxxx 15 0 mmmm: Indirect post-increment register Control register or system register LDC.L @Rm+,SR mmmm: Indirect register — JMP @Rm mmmm: PC relative using Rm — BRAF Rm |
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