SH7203 datasheet(86/1686 Pages) RENESAS

부품명	SH7203

상세설명	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1686 Pages

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제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

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Section 2 CPU

Rev. 2.00 Apr. 16, 2008 Page 56 of 1652

REJ09B0313-0200

Addressing

Mode

Instruction

Format

Effective Address Calculation

Equation

The 20-bit immediate data (imm) for the MOVI20

instruction is sign-extended.

Sign-

extended

imm (20 bits)

—

Immediate

#imm:20

The 20-bit immediate data (imm) for the MOVI20S

instruction is shifted by eight bits to the left, the

upper bits are sign-extended, and the lower bits are

padded with zero.

Sign-extended

imm (20 bits) 00000000

31 27

—

#imm:8

The 8-bit immediate data (imm) for the TST, AND,

OR, and XOR instructions is zero-extended.

—

#imm:8

The 8-bit immediate data (imm) for the MOV, ADD,

and CMP/EQ instructions is sign-extended.

—

#imm:8

The 8-bit immediate data (imm) for the TRAPA

instruction is zero-extended and then quadrupled.

—

#imm:3

The 3-bit immediate data (imm) for the BAND, BOR,

BXOR, BST, BLD, BSET, and BCLR instructions

indicates the target bit location.

—

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