SH7606 datasheet(73/532 Pages) RENESAS

부품명	SH7606

상세설명	32-Bit RISC Microcomputer SuperH??RISC engine Family / SH7606 Series

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제조업체	RENESAS [Renesas Technology Corp]

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Section 2 CPU

Rev. 4.00 Sep. 13, 2007 Page 47 of 502

REJ09B0239-0400

Instruction

Operation

Code

Execution

Cycles

T Bit

STS

MACL,Rn

MACL

→ Rn

0000nnnn00011010



STS

PR,Rn

→ Rn

0000nnnn00101010



STS.L MACH,@

–Rn

Rn–4

→ Rn, MACH → (Rn) 0100nnnn00000010



STS.L MACL,@

–Rn

Rn–4

→ Rn, MACL → (Rn) 0100nnnn00010010



STS.L PR,@

–Rn

Rn–4

→ Rn, PR → (Rn)

0100nnnn00100010



TRAPA #imm

/SR → Stack area,

(imm

× 4 + VBR) → PC

11000011iiiiiiii



Note:

Number of execution cycles until this LSI enters sleep mode.

About the number of execution cycles:

The table lists the minimum number of execution cycles. In practice, the number of

execution cycles will be increased depending on the conditions such as:

• When there is a conflict between instruction fetch and data access

• When the destination register of a load instruction (memory → register) is also used

by the instruction immediately after the load instruction.

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