SH7616 datasheet(30/935 Pages) RENESAS

30 / 935 page

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 4 of 906

REJ09B0292-0200

Item

Specifications

Cache

• Mixed instruction/data type cache

• Maximum of 4 kbytes

• 4-way set-associative type

• 16-byte line length

• 64 cache tag entries

• 16-byte write-back buffer

• Selection of write-through or write-back mode for data writes

• LRU replacement algorithm

• Can also be used as 2-kbyte cache and 2-kbyte RAM (2-way cache mode)

• Mixed instruction/data cache, instruction cache, or data cache mode can

be set

• 1-cycle reads, 2-cycle writes (in write-back mode)

Interrupt controller

(INTC)

• 16 priority levels can be set

• On-chip supporting module interrupt vector numbers can be set

• 41 internal interrupt sources

• The E-DMAC interrupt (EINT) is input to the INTC as the OR of 22 EtherC

and E-DMAC interrupt sources (max.). Thus, from the viewpoint of the

INTC, there is one EtherC/E-DMAC interrupt source.

• Five external interrupt pins (NMI, IRL0 to IRL3)

• 15 external interrupt sources (encoded input) can also be selected for pins

IRL0 to IRL3 (IRL interrupts)

• IRL interrupt vector number setting can also be selected (selection of auto

vector or external vector)

• Provision for IRQ interrupt setting (low-level, rising-edge, falling-edge,

both-edge detection)

SH7616 데이터시트(PDF) 30 Page - Renesas Technology Corp