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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7672 데이터시트(PDF) 98 Page - Renesas Technology Corp |
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SH7672 데이터시트(HTML) 98 Page - Renesas Technology Corp |
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98 / 1292 page  Section 2 CPU Rev. 1.00 Nov. 14, 2007 Page 72 of 1262 REJ09B0437-0100 2.5 Processing States The CPU has five processing states: reset, exception handling, bus-released, program execution, and power-down. Figure 2.6 shows the transitions between the states. Power-on reset from any state Manual reset from any state Power-on reset state Manual reset state Program execution state Sleep mode Software standby mode Exception handling state Exception handling source occurs Exception handling ends NMI interrupt or IRQ interrupt occurs Power-down state Reset canceled STBY bit cleared for SLEEP instruction Reset state Interrupt source or DMA address error occurs STBY and DEEP bits set for SLEEP instruction Bus-released state Bus request generated Bus request cleared Bus request generated Bus request cleared Bus request cleared Bus request generated Figure 2.6 Transitions between Processing States |
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