M32CSLASH8A datasheet(63/372 Pages) RENESAS

63 / 372 page

M32C/8A Group

7. Processor Mode

Rev.1.00

Jul 15, 2007

Page 46 of 352

REJ09B0385-0100

Figure 7.1

PM0 Register

b6 b5 b4

Processor Mode Register 0(1)

Symbol

PM0

Address

0004h

Bit Symbol

Bit Name

PM00

After Reset

0000 0011b (CNVSS = "H")

Function

Processor mode bits(2)

PM01

b1 b0

1 1: Microprocessor mode

Do not set to values other than the above.

PM02

R/W mode select bit

0: RD/BHE/WR

1: RD/WRH/WRL

PM03

Software reset bit

The MCU is reset when this bit is set to 1.

Read as 0.

PM04

PM05

Reserved bit

Set to 0

Multiplexed bus space

select bits(3)

b5 b4

0 0: Multiplexed bus is not used

0 1: Access the CS2 area using multiplexed bus

1 0: Access the CS1 area using multiplexed bus

1 1: Do not set to this value.

ー

(b6)

BCLK output function select bit

0: BCLK output (4)

1: No BCLK output

PM07

NOTES:

1. Set the PM0 register after the PRC1 bit in the PRCR register is set to 1 (write enable).

2. Bits PM01 and PM00 maintain values set before reset, even after software reset or watchdog timer reset has performed.

3. The PM05 and PM04 bits setting is enabled in microprocessor mode. Set these bits in the combination with bits PM11 and PM10

in the PM 1 register. Refer to the Table "Multiplexed Bus Settings and Chip-Select Areas" in the Bus chapter.

4. To output BCLK from P5_3 in microprocessor mode, set the PM07 bit to 0, bits CM01 and CM00 in the CM0 register to "00b" (I/O

port P5_3), and bits PM15 and PM14 in the PM1 register to 00b, 10b, or 11b.

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