M32CSLASH8A datasheet(128/372 Pages) RENESAS

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M32C/8A Group

11. Interrupts

Rev.1.00

Jul 15, 2007

Page 111 of 352

REJ09B0385-0100

11.7

INT Interrupt

External input to pins INT0 to INT5 generate the INT0 to INT5 interrupts. INT interrupts can select either edge

sensitive, which the rising/falling edge triggers an interrupt request, or level sensitive, which an input signal level

to the INTi pin (i = 0 to 5) triggers an interrupt request.

To use INT interrupts with edge sensitive, set the LVS bit in the INTiIC register to 0 (edge sensitive), and select a

rising edge, falling edge, or both edges using the POL bit in the INTiIC register and the IFSRi bit in the IFSR

selected edge is detected at the INTi pin, the corresponding IR bit becomes 1.

To use INT interrupts with level sensitive, set the LVS bit to 1 (level sensitive) and select either “L” level or “H”

level using the POL bit. Also, set the IFSRi bit to 0 (one edge). While the selected level is detected at the INTi pin,

the IR bit becomes 1 and remains 1. Therefore, the interrupt requests are generated repeatedly as long as the

selected level is detected to the INTi pin. When the input signal is changed to the inactive level, the IR bit becomes

0 by the interrupt request acknowledgement or writing a 0 by program.

Interrupts can be enabled or disabled using bits ILVL2 toILVL0 in the INTiIC register.

Figure 11.11 shows INTi interrupt setting procedures (i = 0 to 5). Figure 11.12 shows the IFSR register.

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