M32CSLASH8A datasheet(218/372 Pages) RENESAS

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M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 201 of 352

REJ09B0385-0100

Figure 17.5

U0SMR3 to U4SMR3 Registers

b7 b6 b5 b4

Symbol

U0SMR3 to U2SMR3

U3SMR3, U4SMR3

Address

0365h, 02E5h, 0335h

0325h, 02F5h

After Reset

00h

Function

Bit Symbol

Bit Name

DINC

CKPH

SSE

DL0

DL1

0: CLKi is CMOS output

1: CLKi is N-channel open drain output

Clock output select bit

SS function enable bit(1)

ERR

NODC

0: No mode error

1: Mode error occurred(3)

Mode error flag(1)

SDAi output is delayed by the following cycles.

b7 b6 b5

0 0 0: No delay

0 0 1: 1-to-2 cycles of BRG count source

0 1 0: 2-to-3 cycles of BRG count source

0 1 1: 3-to-4 cycles of BRG count source

1 0 0: 4-to-5 cycles of BRG count source

1 0 1: 5-to-6 cycles of BRG count source

1 1 0: 6-to-7 cycles of BRG count source

1 1 1: 7-to-8 cycles of BRG count source

SDAi digital delay set bits(4, 5)

DL2

UARTi Special Mode Register 3 (i = 0 to 4)

Clock phase set bit(1)

Serial input pin set bit(1)

0: No Clock delay

1: Clock delay

0: Pins TXDi and RXDi selected (master mode)

1: Pins STXDi and SRXDi selected (slave mode)

0: SS function disabled

1: SS function enabled(2)

NOTES:

1. These bits are used in special mode 2.

2. When the SS pin is set to 1, set the CRD bit in the UiC0 register to 1 ( CTS function disabled).

3. The ERR bit is set to 0 by writing a 0. Writing a 1 has no effect.

4. Digital delay is added to a SDAi output using bits DL2 to DL0 in I 2C mode. Set them to 000b (no delay) in other than I 2C mode.

5. When the external clock is selected, SDAi output is delayed by approximately 100 ns in addition.

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