M32CSLASH8A datasheet(228/372 Pages) RENESAS

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M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 211 of 352

REJ09B0385-0100

Figure 17.13

Receive Operations when External Clock is Selected

TE bit in the

UiC1 register

i = 0 to 4

fEXT = external clock frequency

The above applies under the following conditions:

- UiMR register: CKDIR bit = 1 (external clock)

- UiC0 reigster: CRD bit = 1 (CTS function disabled)

CKPOL bit = 0 (receive data input at the rising edge of the serial clock)

NOTE:

1. Satisfy the following conditions, while the CLKi pin input is "H" before the data receive operation.

- UiC1 register: TE bit = 1 (transmit operation enabled)

RE bit = 1 (receive operation enabled)

- Write dummy data to the UiTB register

TI bit in the UiC1

Write dummy data to UiTB register

RTSi output

“H”

“L”

CLKi input(1)

RXDi input

RI bit in the

UiC1 register

IR bit in the SiRIC

Set to 0 by an interrupt request acknowledgement or by program

RE bit in the

UiC1 register

OER bit in the

UiRB register

fEXT

D0 D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5

“H”

“L”

“H”

“L”

Transfer data from UiTB register

to UARTi transmit shift register

Becomes "L" by reading UiRB register

Transfer data from UARTi

receive shift register to UiRB

A read from UiRB register

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