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H8S2245 데이터시트(PDF) 370 Page - Renesas Technology Corp

부품명 H8S2245
상세설명  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.3.00 Mar. 26, 2007 Page 328 of 772
REJ09B0355-0300
9.4.4
Buffer Operation
Buffer operation, provided for channel 0 enables TGRC and TGRD to be used as buffer registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 9.5 shows the register combinations used in buffer operation.
Table 9.5
Register Combinations in Buffer Operation
Channel
Timer General Register
Buffer Register
0TGR0A
TGR0C
TGR0B
TGR0D
When TGR is an output compare register: When a compare match occurs, the value in the
buffer register for the corresponding channel is transferred to the timer general register.
This operation is illustrated in figure 9.16.
Buffer register
Timer general
register
TCNT
Comparator
Compare match signal
Figure 9.16 Compare Match Buffer Operation
When TGR is an input capture register: When input capture occurs, the value in TCNT is
transferred to TGR and the value previously held in the timer general register is transferred to the
buffer register.
This operation is illustrated in figure 9.17.



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