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H8S2245 데이터시트(PDF) 383 Page - Renesas Technology Corp

부품명 H8S2245
상세설명  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
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Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.3.00 Mar. 26, 2007 Page 341 of 772
REJ09B0355-0300
9.5
Interrupts
9.5.1
Interrupt Sources and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 9.12 lists the TPU interrupt sources.
Table 9.12
TPU Interrupts
Channel
Interrupt
Source
Description
DTC
Activation
Priority
TGI0A
TGR0A input capture/compare match
Possible
High
TGI0B
TGR0B input capture/compare match
Possible
TGI0C
TGR0C input capture/compare match
Possible
TGI0D
TGR0D input capture/compare match
Possible
0
TCI0V
TCNT0 overflow
Not possible
TGI1A
TGR1A input capture/compare match
Possible
TGI1B
TGR1B input capture/compare match
Possible
TCI1V
TCNT1 overflow
Not possible
1
TCI1U
TCNT1 underflow
Not possible
TGI2A
TGR2A input capture/compare match
Possible
TGI2B
TGR2B input capture/compare match
Possible
TCI2V
TCNT2 overflow
Not possible
2
TCI2U
TCNT2 underflow
Not possible
Low
Note:
This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.



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