H8S2245 datasheet(550/818 Pages) RENESAS

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Section 14 A/D Converter

Rev.3.00 Mar. 26, 2007 Page 508 of 772

REJ09B0355-0300

14.2.2

A/D Control/Status Register (ADCSR)

ADF

R/(W)*

ADIE

R/W

ADST

R/W

SCAN

R/W

CKS

R/W

CH0

R/W

—

R/W

CH1

R/W

Bit

Initial value

R/W

Note: * Only 0 can be written to bit 7, to clear this flag.

ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows

the status of the operation.

ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode.

Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.

Bit 7

ADF

Description

[Clearing conditions]

(Initial value)

• When 0 is written to the ADF flag after reading ADF = 1

• When the DTC* is activated by an ADI interrupt and ADDR is read

[Setting conditions]

• Single mode: When A/D conversion ends

• Scan mode: When A/D conversion ends on all specified channels

Note:

The flag is cleared only when DISEL in DTC is 0 and the transfer counter value is not 0.

Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests

at the end of A/D conversion.

Bit 6

ADIE

Description

A/D conversion end interrupt (ADI) request disabled

(Initial value)

A/D conversion end interrupt (ADI) request enabled

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